1. Field of the Invention
The present invention relates to the field of fabricating semiconductor devices including circuit elements, such as field effect transistors (FETs), and, in particular, to a method and system for improved control of the manufacturing process of circuit elements to more reliably stabilize an electrical property of the completed devices.
2. Description of the Related Art
The dimensions of modern integrated circuits are steadily shrinking, while at the same time providing both improved device performance and circuit density. Both advantages are mainly obtained by steadily shrinking the feature sizes of the individual field effect transistor elements, such as MOS transistors, whereby critical dimensions, i.e., minimum feature sizes that can be reproducibly printed onto the substrate, are currently approaching the 0.1 μm range, and further reductions are anticipated in the future. The formation of modern ultra-high density integrated circuits may require approximately 500 individual process steps, wherein one of the most critical steps is the formation of the gate electrode of the field effect transistors. The gate electrode controls, upon application of a suitable control voltage such as 2-3 volts or even less in modern CPUs, the current flow through a channel that forms below a thin gate insulation layer separating the gate electrode from the underlying semiconductor region. Generally, the gate electrode is designed to have a width dimension on the order of micrometers and less and a length dimension, also referred to as gate length, currently on the order of 0.1 μm. This gate length, which represents the distance between the highly doped source and drain regions of the field effect transistor, significantly affects the device performance with respect to signal propagation time and current flow from the source to the drain. Trimming the gate length down to a size of about 0.1 μm necessitates an enormous effort to establish an appropriate lithography technique and a sophisticated etch trim method, wherein any deviation from a target value of the gate length significantly contributes to a variation of the electrical properties of the completed transistor element. In particular, the on-current and the off-current, i.e., the current that flows when a conductive channel is formed between the source and the drain region and the current that flows when the conductive channel is not formed, as well as the switching speed, are greatly influenced by the gate length.
Generally, a reduced gate length leads to an increased on-current and to an increased switching speed of the transistor element. At the same time, however, the off-current, i.e., the undesired leakage current, also increases with a smaller gate length owing to an increased electrical field in the vicinity of the gate electrode. Accordingly, a reduced gate length compared to the target value, although improving speed of the transistor element, may result in a lower yield of the completed transistor elements due to the increased and thus intolerable leakage current. On the other hand, an increased gate length compared to the target value enhances the transistor characteristics with respect to leakage current, but entails a lower on-current and a lower speed of the transistor. As a consequence, circuit designers have to take into account the variation of the electrical properties of the individual transistor elements owing to manufacturing tolerances in forming elements of critical dimensions, thereby posing constraints on the performance of the entire circuit.
As a consequence, process engineers are making great efforts to develop process control strategies to reduce fluctuations of the individual process steps as much as possible to achieve a high performance of the end product. To this end, so-called advanced process control (APC) methods are steadily being designed and enhanced, in which typically pre-process inline data and post-process inline data are analyzed and used to control the process under consideration with minimal time delay, preferably on a run-to-run basis. However, at least some important device characteristics, such as operational speed, depend on a plurality of process steps, wherein a slight deviation in some of the processes, although well within a tight process window for each process, may still result in a significant deviation of the desired behavior of the device, for instance in terms of speed, yield, reliability and the like.
In view of the above problems, a need exists for an enhanced control scheme to more efficiently control product parameters and electrical properties such as the on-current and the off-current, the switching speed and the like during fabrication of the field effect transistors.